USB7006SLASHKDX datasheet(21/56 Pages) MICROCHIP

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DS00003715B-page 21

USB7006

3.4

Physical and Logical Port Mapping

The USB70xx family of devices are based upon a common architecture, but all have different modifications and/or pin

bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7

USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL

port mapping.

The actual port numbering is remapped by default in different ways on each device in the family. This changes the way

that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping.

The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or

LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared

as such within the register description.

The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics

and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default

LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when

determining the hub configuration.

PRT_CTL5_U3

O12

Port 5 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the

USB 3.2 portion of the downstream port 5 when PortSplit is

enabled. When PortSplit is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded

USB 3.2 device.

Float

PRT_CTL4_U3

O12

Port 4 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the

USB 3.2 portion of the downstream port 4 when PortSplit is

enabled. When PortSplit is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded

USB 3.2 device.

Float

PRT_CTL3_U3

O12

Port 3 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the

USB 3.2 portion of the downstream port 3 when PortSplit is

enabled. When PortSplit is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded

USB 3.2 device.

Float

Note:

The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect

to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings.

Refer to Section 6.0, Device Configuration for additional information.

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)

Function

Buffer

Type

Description

If Unused

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