VV5430

Serial Communication

CD5430F-A

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Table 13 : Serial Interface Timing Characteristics

Parameter

Symbol

Min.

Max.

Unit

SCL clock frequency

0100

kHz

Bus free time between a

stop and a start

4.7

-

µs

Hold time for a repeated

start

4.0

-

µs

LOW period of SCL

4.7

-

µs

HIGH period of SCL

4.0

-

µs

Set-up time for a repeated

start

4.7

-

µs

Data hold time

0

1

1. The VV5430 internally provides a hold time of at least 300ns for the SDA signal (referred

to the minimum input level (high) of the SCL signal) to bridge the undefined region of the

falling edge of SCL

-µs

Data Set-up time

250

-

ns

Rise time of SCL, SDA

-1000

ns

Fall time of SCL, SDA

-300

ns

Set-up time for a stop

4.0

-

µs

Capacitive load of each

bus line (SCL, SDA)

-100

pF

SDA

SCL

...

...

stop

start

stop

start

Note: All values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V