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LP3941A Arkusz danych(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części LP3941A
Szczegółowy opis  Cellular Phone Power Management Unit
PDF  32 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

LP3941A Arkusz danych(HTML) 3 Page - National Semiconductor (TI)

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Pin Description
Pin #
Name
I/O
Type
Description
1
N/C
-
-
Not used. Connect to ground.
2
AGND3
G
G
Analog ground pin.
3V
O8
O
A
LDO 8 Output
4
IN5
I
P
Input power terminal to LDO’s. Must be connected to IN1–4 and IN6.
5V
O9
O
A
LDO 9 output.
6V
O10
O
A
LDO 10 output.
7
IN6
I
P
Input power terminal to LDO’s. Must be connected to IN1–5.
8V
O11
O
A
LDO 11 output.
9
DGND
G
G
Ground pin.
10
V
O3
O
A
LDO 3 output.
11
IN2
I
P
Input power terminal to LDO’s. Must be connected to IN1 and IN3–6.
12
V
O2
O
A
LDO 2 output.
13
IN1
I
P
Input power terminal to LDO’s. Must be connected to IN2–6.
14
V
O1
O
A
LDO 1 output.
15
PS-HOLD
I
D
Active low off key initiated by the micro controller.
16
BU_BAT
I
A
Back-up battery connection.
17
VRTC
O
A
RTC_LDO output.
18
IN (COMP1)
I
A
Non-inverting inout of the comparator 1.
19
OUT (COMP1)
O
A
Output of the comparator 1.
20
AGND1
G
G
Analog ground pin.
21
IN (COMP2)
I
A
Non-inverting input of the comparator 2.
22
OUT (COMP2)
O
A
Output of the comparator 2.
23
REF-BYP
I
A
Reference bypass capacitor.
24
V
O7
O
A
LDO 7 output.
25
V
O6-EN
I
D
LDO 6 on/off pin. Internal pull-down resistor of 1 M
Ω.
26
IN4
I
P
Input power terminal to LDO’s. Must be connected to IN1–3 and IN5–6.
27
V
O6
O
A
LDO 6 output.
28
V
O5
O
A
LDO 5 output.
29
IN3
I
P
Input power terminal to LDO’s. Must be connected to IN1–2 and IN4–6.
30
V
O4
O
A
LDO 4 output.
31
BSNS
I
A
Main battery ID resistor connection.
32
ON
O
OD
Inverted open drain output signal of the ON input. Pulled low when ON is
pulled high and open drain when ON is pulled low. There is no significant
delay between the ON signal going high and ON pin going low. The delay
between ON signal going low and ON pin is determined by the pull up current
and capacitance connected to this pin.
33
BATT
SENSE
I
A
Battery voltage sense pin. Should be connected as close to the battery’s +
terminal as possible.
34
Drive
O
A
Gate drive to the external MOSFET.
35
BATT
O
A
Battery supply input terminal. Must have 10 µF ceramic capacitor to GND.
36
V
O5-EN
I
D
LDO 5 on/off pin. Internal pull down resistor of 1 M
Ω.
37
RTC_ALARM
I
D
RTC_ALARM input.
38
ON
I
D
Active high power On/Off key. This pin is pulled to GND by an internal 200
k
Ω resistor.
39
HF_PWR
I
D
Active high Hands Free connection signal. This pin has an internal 200 k
Ω
pull down resistor.
40
CHG_IN
I
P
Charger input from a current limited power source. Must havea1µF ceramic
capacitor to GND.
41
I
SENSE
O
A
Charge current sense resistor.
42
RESET
O
OD
Reset output. Active low. (See Power Up Timing Diagram.)
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