MCP4921 datasheet(17/40 Pages) MICROCHIP

17 / 40 page

 2004 Microchip Technology Inc.

DS21897A-page 17

MCP4921/4922

4.1

Circuit Descriptions

4.1.1

OUTPUT AMPLIFIERS

The DACs’

outputs are buffered with a low-power,

precision CMOS amplifier. This amplifier provides low

offset voltage and low noise. The output stage enables

the device to operate with output voltages close to the

power supply rails. Refer to Section 1.0 “Electrical

Characteristics” for range and load conditions.

In addition to resistive load driving capability, the ampli-

fier will also drive high capacitive loads without oscilla-

tion. The amplifiers’ strong outputs allow VOUT to be

used as a programmable voltage reference in a

system.

Selecting a gain of 2 reduces the bandwidth of the

amplifier in Multiplying mode. Refer to Section 1.0

“Electrical Characteristics” for the Multiplying mode

bandwidth for given load conditions.

4.1.1.1

Programmable Gain Block

The rail-to-rail output amplifier has configurable gain

allowing optimal full-scale outputs for differing voltage

reference inputs. The output amplifier gain has two

selections, a gain of 1 V/V (GA = 1) or a gain of 2 V/V

(GA = 0).

The output range is ideally 0.000V to 4095/4096 * VREF

when G = 1, and 0.000 to 4095/4096 * VREF when

G = 2. The default value for this bit is a gain of 2, yield-

ing an ideal full-scale output of 0.000V to 4.096V when

utilizing a 2.048V VREF. Note that the near rail-to-rail

CMOS output buffer’s ability to approach AVSS and

VDD establish practical range limitations. The output

swing specification in Section 1.0 “Electrical Charac-

teristics” defines the range for a given load condition.

4.1.2

VOLTAGE REFERENCE

AMPLIFIERS

The input buffer amplifiers for the MCP492X devices

provide low offset voltage and low noise. A configura-

tion bit for each DAC allows the VREF input to bypass

the input buffer amplifiers, achieving a Buffered or

Unbuffered mode. The default value for this bit is

unbuffered. Buffered mode provides a very high input

impedance, with only minor limitations on the input

range and frequency response. Unbuffered mode

provides a wide input range (0V to VDD), with a typical

input impedance of 165 k

Ω w/7 pF.

4.1.3

POWER-ON RESET CIRCUIT

The Power-On Reset (POR) circuit ensures that the

DACs power-up with SHDN = 0 (high-impedance). The

devices will continue to have a high-impedance output

until a valid write command is performed to either of the

DAC registers and the LDAC pin meets the input low

threshold.

If the power supply voltage is less than the POR

threshold (VPOR = 2.0V, typical), the DACs will be held

in their reset state. They will remain in that state until

VDD > VPOR and a subsequent write command is

received.

Figure 4-3 shows a typical power supply transient

pulse and the duration required to cause a reset to

occur, as well as the relationship between the duration

and trip voltage. A 0.1 µF decoupling capacitor

mounted as close as possible to the VDD pin provides

additional transient immunity.

FIGURE 4-3:

Typical Transient

Response.

4.1.4

SHUTDOWN MODE

Shutdown mode can be entered by using either hard-

ware or software commands. The hardware pin

(SHDN) is only available on the MCP4922. During

Shutdown mode, the supply current is isolated from

most of the internal circuitry. The serial interface

remains active, thus allowing a write command to

bring the device out of Shutdown mode. When the

output amplifiers are shut down, the feedback resis-

tance (typically 500 k

Ω) produces a high-impedance

path to AVSS. The device will remain in Shutdown

mode until the SHDN pin is brought high and a write

command with

SD = 1 is latched into the device.

When a DAC is changed from Shutdown to Active

mode, the output settling time takes < 10 µs, but

greater than the standard Active mode settling time

(4.5 µs).

Transients above the curve

will cause a reset

Transients below the curve

will NOT cause a reset

Time

Transient Duration

VPOR

VDD - VPOR

TA = +25°C

123

VDD – VPOR (V)

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