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DAC82002 Arkusz danych(PDF) 6 Page - Texas Instruments |
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DAC82002 Arkusz danych(HTML) 6 Page - Texas Instruments |
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6 / 22 page ![]() 6.6 Timing Requirements all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.15 V, 2.0 V ≤ VREF ≤ 5.5 V, and TA = –40°C to +85°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency 50 MHz tSCLKHIGH SCLK high time 9 ns tSCLKLOW SCLK low time 9 ns tSDIS SDIN setup 5 ns tSDIH SDIN hold 10 ns tSYNCS SYNC falling edge to SCLK falling edge setup 13 ns tSYNCH SCLK falling edge to SYNC rising edge 10 ns tSYNCHIGH SYNC high time 160 ns tSYNCIGNORE SCLK falling edge to SYNC ignore 15 ns tDACWAIT Sequential DAC update wait time 1 µs 6.7 Timing Diagram t SYNCS t SDIS t SDIH SYNC SDIN t SYNCHIGH Bit 23 t SCLKLOW Bit 1 Bit 0 t SYNCH SCLK t SCLKHIGH t SYNCIGNORE Figure 6-1. Timing Diagram DAC82002 SBASAK1 – AUGUST 2022 www.ti.com 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82002 |
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