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MPFS095T Arkusz danych(PDF) 29 Page - Microchip Technology |
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MPFS095T Arkusz danych(HTML) 29 Page - Microchip Technology |
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29 / 50 page ![]() Figure 4-2. Transceiver Lane Modes TX Fabric Interface TX PMA TX PCS RX PMA Tx PLL Reference Clock Network RX PCS Polarity RX Fabric Interface To PCIe Controller EQ FELB or NELB 8b10b Encoder 64b/6xb Encoder PCIe/SATA PIPE Pre/Post Emphasis Serializer PCS Divider OOB Electrical Idle PMA Polarity CTLE Eye Diagram Jitter Attenuation or Spread Spectrum Frac-N PLL 8b10b Decoder 64b/6xb Decoder PCIe/SATA PIPE PMA PCS Divider CDR w DFE Deserializer ÷ 1, 2, 4, 8, 11 From PCIe Controller CDR FELB LB FIFO Programmable Logic Subsystem © 2021 Microchip Technology Inc. and its subsidiaries Overview DS60001656C-page 29 |
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