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ATO25F1GC-30EC Arkusz danych(PDF) 21 Page - List of Unclassifed Manufacturers |
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ATO25F1GC-30EC Arkusz danych(HTML) 21 Page - List of Unclassifed Manufacturers |
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21 / 46 page ![]() 21/46 Sep.2013. Rev 0.5 1Gbit Serial NAND Flash Memory 8.2 Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion OTP program instruction completion Page Program (PP) instruction completion Block Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence SCLK CS# 0 1 2 3 4 5 6 7 Mode3 Mode0 Mode3 Mode0 Instruction (04h) SI SO High Impedance |
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