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SH79F6489P/080PR Arkusz danych(PDF) 82 Page - SINOWEALTH Electronic Ltd |
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SH79F6489P/080PR Arkusz danych(HTML) 82 Page - SINOWEALTH Electronic Ltd |
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82 / 152 page ![]() SH79F6488/SH79F6489 82 8.3.3 Baud Rate In master mode, the baud rate is chosen from one of the six clock rates by the division of the internal clock by 4, 8, 16, 32, 64 or 128 set by the three bits SPR[2:0] in the SPCON register. 8.3.4 Functional Description The following diagram shows a detailed structure of the SPI module. Internal Bus Clock Divider /128 /4 /8 /16 /32 /64 Clock Select Clock Logic SPI Control DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 SPEN SPIF MODF WCOL RXOV - - - SPSTA Pin Control Logic MOSI MISO SCK SS M S FCLK PERIPH Recieve Data Register SPI Interrupt Request 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Recieve Register Transmit Register SPDAT 8-bit Bus 1-bit Signal SPI Module Block Diagram |
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