L9679E datasheet(77/124 Pages) STMICROELECTRONICS

77 / 124 page

Figure 18. High-level loop diagnostic flow 1

Low level diagnostic is selected (bit 15

of LPDIAGREQ is low) OR an invalid

high level diagnostic is selected OR we

are in DEP_ENABLED state

Leakage test time elapsed

SBL flag is asserted if STG

is no more present

AND (FET test is selected)

AND NO leakage is present

Leakage test time elapsed

AND ((LEAKAGE test) OR

(SBL and no leakage is

present) OR (FET test and

leakage is present))

Latch STB, STG flags

FP = 1 if FET test is selected

VRCM (check time elapsed

AND ((VRCM, CHECK test)

is selected OR VRCM fails)

VRCM (check time elapsed

AND (LEAKAGE OR SBL

OR FET test is selected)

AND VRCM NO fails

Latch STB, STG flags

FP = 1 if LEAKAGE or

FET T tests are selected

Leakage test time elapsed

AND (SBL is selected)

AND leakage is present

TIP = 1

Enable VRCM

Disable ISRC and

ISINK

Disable ALL pull

down currents

TIP = 1

TIP = 0

Enable VRCM

Disable ISRC and ISINK

TIP = 1

Enable VRCM

Disable ISRC and ISINK

TIP = 1

Enable VRCM

Disable ISRC and ISINK

Enable HS or LS FET if also

DSTEST = 0111 or 1000

TIP = 1

Off time elapsed AND new

diagnostic request is

VRCM_CHECK OR

LEAKAGE OR SBL OR

FET tests

Off time = 24 µs

New high level diagnostic request

(bit 15 of LPDIAGREQ is high)

Wait enaugh time to

be sure that all

currents and voltages

supplies start in OFF state

FET test timeout = 200µs

Leakage test time = 152/600µs

FET TEST

DIAG_OFF

WAIT_OFF

LEAKAGE_TEST_1

LEAKAGE_TEST_2

VRCM check time = 40µs/160µs

VRCM_CHECK

Leakage is detected (due to

the fact that FETs work

properly) OR FET test

timeout elapsed

GADG0903181321PS

L9679E

Diagnostics

DS12485 - Rev 5

page 77/124

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