DS12849 Rev 1

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STA8089GR

General description

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3

General description

3.1

RF front end

The RF front-end is able to down-convert both the GPS signal from 1575.42 MHz to

4.092 MHz (4 Fo, being F0 = 1.023 MHz), the GLONASS signal from 1601.718 MHz to

8.57 MHz and the BeiDou signal from 1561.098 MHz to 10.23 MHz.

It embeds high performance LNA minimizing external component count and a LDO to

supply the internal core facilitating requirements for external power supply. A three bits ADC

converts the IF signals to sign (SIGN) and magnitude (MAG0 and MAG1). They can be

sampled or not by SPI. The magnitude bits are internally integrated in order to control the

variable gain amplifiers. The VGA gain can be also set by the SPI interface.

The RF tuner accepts a wide range of reference clocks (10 to 52 MHz) and can generate

64 Fo sampling clock for the baseband and 192 Fo clock for MCU subsystem.

3.2

GPS/GLONASS/BeiDou Base Band (G3BB+) processor

STA8089GR integrates G3BB+ proprietary IP, which is the ST last generation high-

sensitivity Baseband processor fully compliant with GPS, GLONASS and BeiDou systems.

The baseband receives, from the embedded RF Front-End, two separate IF signals coded

in sign-magnitude digital format on 3 bits and the related clocks. The GPS and

GLONASS/BeiDou (GNSCOM) signals at the base band inputs are centered on 4.092 MHz,

8.57 MHz and 10.23 MHz.

The baseband processes the two IF signals performing data codification, sample rate

conversion and final frequency conversion to zero IF before acquisition and tracking

correlations.

The baseband processor has the capability of acquire and track the GPS, GLONASS and

BeiDou signals in a simultaneous or single way, or a combination of three, being GLONASS

and BeiDou mutually exclusive. The number of tracking channels to be used is

programmable; the not used tracking channels can be powered down.

A complete multi-OS software library is provided by ST to handle GPS processing,

managing satellite acquisition, tracking, pseudo-range calculation and positioning,

generating the output in the standard NMEA message format. The library includes support

for server-based ephemeris extension.

3.3

MCU Subsystem

The implemented sub-system includes an AHB Lite bus matrix.

An ARM946 core is embedded in the sub-system and masters the AHB bus. The totally

available TCM SRAM is 256 KB. The amount of memory on ITCM and DTCM can be

configured by the ARM946 (see Table 6: TCM Configuration). ITCM can be configured as Ni

x 16 KB; DTCM can be configured as 128 + Nd x 16 KB, where Ni + Nd = 8, Ni

1.