CS47L35 datasheet(7/300 Pages) CIRRUS

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DS1085F3

CS47L35

1.2 Pin Descriptions

CIF2SDA

N11

DBVDD1

I/O

Control interface 2 (I2C) data input and output. The SDA output is

open drain.

IRQ

DBVDD1

Interrupt request output (default is active low). The pin configuration

is selectable CMOS or open drain.

MCLK1

M12

DBVDD1

Master clock 1

MCLK2

DBVDD2

Master clock 2

MIF1SCLK/GPIO16

DBVDD1

I/O

Master (I2C) Interface 1 clock output/GPIO. GPIO output is

selectable CMOS or open drain; SCLK output is open drain.

MIF1SDA/GPIO7

DBVDD1

I/O

Master (I2C) Interface 1 data input and output/GPIO. GPIO output is

selectable CMOS or open drain; SDA output is open drain.

RESET

DBVDD1

Digital reset input (active low)

SLIMCLK

DBVDD1

I/O

SLIMbus clock I/O

SLIMDAT

DBVDD1

I/O

SLIMbus data I/O

SPKCLK/GPIO6

DBVDD2

I/O

Digital speaker (PDM) 1 clock output/GPIO. GPIO output is

selectable CMOS or open drain; SPKCLK output is CMOS.

SPKDAT/GPIO5

DBVDD2

I/O

Digital speaker (PDM) 1 data output/GPIO. GPIO output is selectable

CMOS or open drain; SPKDAT output is CMOS.

TCK

DBVDD2

JTAG clock input. Internal pull-down holds this pin at Logic 0 for

normal operation.

TDI

DBVDD2

JTAG data input. Internal pull-down holds this pin at Logic 0 for

normal operation.

TDO

DBVDD2

JTAG data output

TMS

DBVDD2

JTAG mode select input. Internal pull-down holds this pin at Logic 0

for normal operation.

TRST

DBVDD2

JTAG test access port reset (active low). Internal pull-down holds this

pin at Logic 0 for normal operation.

Supply

AGND1

—

Analog ground (return path for AVDD1)

AGND2

E9, G11

—

Analog ground (return path for AVDD2)

AVDD1

—

Analog supply

AVDD2

F12

—

Analog supply

CPGND

—

Charge pump ground (return path for CPVDD1, CPVDD2)

CPVDD1

—

Supply for Charge Pump 1 and Charge Pump 2

CPVDD2

—

Secondary supply for Charge Pump 1

DBVDD1

U11

—

Digital buffer (I/O) supply

(core functions, AIF1, CIF1, CIF2, SLIMbus, MIF1)

DBVDD2

—

Digital buffer (I/O) supply

(AIF2, AIF3, PDM, MCLK2, JTAG)

Table 1-1. Pin Descriptions (Cont.)

Name

Ball #

Power

Supply

I/O

Description

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