SCAS641

– JULY 2000

2

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

The HOST bus operates at 100 MHz or 133 MHz. The MREF bus operates at 50 MHz or 66 MHz. Output

frequency selection is accomplished with corresponding setting for SEL100/133 control input. The PCI bus

frequency is fixed to 33 MHz.

Since the CDC930 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up as well as changes to SEL inputs. With use of external

reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time starts.

functional block diagram

Control

Logic

3-State/Low

Test

SEL 100/133

Latched

2

Xtal

Oscillator

/3

/2

CPU

PLL

Spread

Logic

/2

48 MHz

PLL

/2

180

Phase

Shift

Latched

2

2*REF

14.318 MHz

(2,3)

2*3V48

48 MHz

(25,26)

10*PCI

33 MHz

(8,9,11,12,14,

15,17,18,20,21)

4*3V66

66 MHz

(30,31,34,35)

1*3VMREF

50/66 MHz

(55)

1*3VMREF

50/66 MHz

(54)

4*HCLK

100/133 MHz

(42,45,48,51)

4*HCLK

100/133 MHz

(41,44,47,50)

23

SEL100/133

25

SELA

26

SELB

5

XIN

6

XOUT

52

SPREAD

28

PWRDWN

2

MultSel0

3

MultSel1

39

I_REF