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VS1003 Arkusz danych(PDF) 21 Page - VLSI Solution Oy |
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VS1003 Arkusz danych(HTML) 21 Page - VLSI Solution Oy |
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21 / 61 page ![]() VS1003 7 SPI BUSES 7.7 SPI Examples with SM_SDINEW and SM_SDISHARED set 7.7.1 Two SCI Writes 0 1 2 3 30 31 1 0 1 0 0 0 0 0 0 0 X X XCS SCK SI 2 32 33 61 62 63 SCI Write 1 SCI Write 2 DREQ DREQ up before finishing next SCI write Figure 13: Two SCI Operations. Figure 13 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between the writes. Also DREQ must be respected as shown in the figure. 7.7.2 Two SDI Bytes 1 2 3 XCS SCK SI 7 6 5 4 3 1 0 7 6 5 2 1 0 X SDI Byte 1 SDI Byte 2 0 6 7 8 9 13 14 15 DREQ Figure 14: Two SDI Bytes. SDI data is synchronized with a raising edge of xCS as shown in Figure 14. However, every byte doesn’t need separate synchronization. Version: 1.09, 2018-03-16 21 |
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