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LM3655 Arkusz danych(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części LM3655
Szczegółowy opis  Charge Control and Protection IC for embedded single
PDF  21 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM3655 Arkusz danych(HTML) 3 Page - National Semiconductor (TI)

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Table of Contents (Continued)
16.0 Physical Dimensions ................................................................................................................................ 21
6.0 Connection Diagrams and Package Marking
20111502
MicroSMD Top View
See NS Package Number TLA25
20111503
MicroSMD Bottom View
7.0 LM3655 Pin Description
Pin #
Name
I/O
Type
Description
A1
CHEMISTRY
Input
Logic
A low input sets the constant voltage and termination voltage to the
lower V
TERML. A high input sets the constant voltage to the higher
voltage level V
TERMH. This pin has an internal 100 k
Ω pull-down
resistor and can be controlled by a peripheral IC or can be tied directly
to B+ or GND.
A2
HIB_DISB
Input
Logic
This pin is internally pulled up to the CELL pin by a 100K resistor.
When this pin is momentarily pulsed low, Hibernate mode is exited,
which turns on M4.
A3
HIB_EN
Input
Analog
The IC is configured in hibernation mode, when this pin is pulled high
after a debounce period. Activating hibernation mode turns off the
internal M4 transistor.
A4
EXT_PWR_ON
Output
Logic
EXT_PWR_ON is a push-pull output. It is a logic 1 (Radio_B+ voltage
level) when the cell has reached the V
phone_on level (nominally 3.0V)
while the charger is connected and the battery is present.
A5
CNTRL
Output
Analog
This output pin regulates the charger current by controlling the base
voltage of the external drive and pass transistors Q2 and Q1.
B1, C1, C2,
D1
RADIO
Output
Analog
This is the power supply terminal for the phone. ALL load current from
the cell must be sourced from this pin.
B2
NC
This pin must be left floating. It needs to be connected to a non
connected PCB pad for heat sinking. It cannot be connected to other
NC pins.
B3, C3, D3
CELL
I/O
Analog
These pins need to be connected to the cell’s positive terminal.
B4, C4, D4
V
IN
Input
Analog
Input from the pass transistor Q1.
B5, C5, D5
GND
Ground
Ground pin for the circuit and CELL-
D2
NC
This pin must be left floating. It needs to be connected to a non
connected PCB pad for heat sinking. It cannot be connected to other
NC pins.
E1
DISABLE
Input
Logic
A logic high applied to this input disables the charging. A logic low
enables it. This pin has an internal 100 K
Ω pull-down resistor and can
be left unconnected.
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