CS5825
Century Semiconductor Inc.
page 6 of 13
Switching Characteristics over recommended operating conditions (unless otherwise noted)
Switching Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tsu2
Setup time, D0 - D20 valid to CLKOUT
↓
CL = 8pF (Figure-3)
5-
-
ns
th2
Hold time, CLKOUT
↓ to D0 - D20 valid
5-
-
ns
tRSKM
Receive input skew margin
tc = 15.38 ns (±0.2%),
Input clock jitter < 50 ps
(Figure-4)
490
-
-
ps
td
Delay time, CLKIN
↑ to CLKOUT ↓
tc = 15.38 ns (±0.2%),
CL = 8 pF
-3.7
-
ns
∆ t
c(o)
Cycle time, change in output clock
period#
-
± 100
-
ps
ten
Enable time, SHTDN
↑ to Dn valid
Figure-6
-
1
-
ms
tdis
Disable time, SHTDN
↓ to off state
Figure-7
-
400
-
ns
tt
Transition time, output (10% to 90% tr or
tf)
CL = 8pF
-
3
-
ns
tw
Pulse duration, output clock
-
-
0.43tc
-ns
Symbol
Parameter
Min
Typ
Max
Unit
LHT
low to high transition time
-2.2
5
ns
HLT
high to low transitions time
-2.2
5
ns
Pos0
input strobe position for bit 0 (f = 65MHz)
0.7
1.1
1.4
ns
Pos1
input strobe position for bit 1 (f = 65MHz)
2.9
3.3
3.6
ns
Pos2
input strobe position for bit 2 (f = 65MHz)
5.1
5.5
5.8
ns
Pos3
input strobe position for bit 3 (f = 65MHz)
7.3
7.7
8.0
ns
Pos4
input strobe position for bit 4 (f = 65MHz)
9.5
9.9
10.2
ns
Pos5
input strobe position for bit 5 (f = 65MHz)
11.7
12.1
12.4
ns
Pos6
input strobe position for bit 6 (f = 65MHz)
13.9
14.3
14.6
ns
SKM
Rxin skew margin (f = 65MHz)
400
-
-
ps
COP
RxCLK OUT Period
14.7
-
32.2
ns
COH
RxCLK OUT high time (f = 65MHz)
7.5
-
-
ns
COL
RxCKK OUT low time (f = 65MHz)
3.5
-
-
ns
SRC
RxOUT setup to RxCLKOUT (f = 65MHz)
2.5
-
-
ns
HRC
RxOUT hold to RxCLKOUT (f = 65MHz)
2.5
-
-
ns
CCD
RxCLK In to RxCLK OUT delay
5-
9
ns
PLLs
Phase Lock Loop set
--
10
ms
PDD
Power down delay
--
1
µs
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