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MPC855T Arkusz danych(PDF) 24 Page - NXP Semiconductors

Numer części MPC855T
Szczegółowy opis  MPC860 PowerQUICC Family Hardware Specifications
PDF  77 Pages
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Producent  NXP [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
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MPC855T Arkusz danych(HTML) 24 Page - NXP Semiconductors

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MPC860 PowerQUICC Family Hardware Specifications, Rev. 10
24
Freescale Semiconductor
Bus Signal Timing
Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in
the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 9. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 10 through Figure 13 provide the timing for the external bus read controlled by various GPCM
factors.
Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00)
CLKOUT
TA
D[0:31],
DP[0:3]
B20
B21
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11
B12
B23
B8
B22
B26
B19
B18
B25
B28



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