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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD6645/PCB Arkusz danych(PDF) 4 Page - Analog Devices |
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AD6645/PCB Arkusz danych(HTML) 4 Page - Analog Devices |
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4 / 20 page  REV. 0 AD6645 –4– SWITCHING SPECIFICATIONS (continued) AD6645ASQ-80 Parameter (Conditions) Name Temp Test Level Min Typ Max Unit ENCODE Input Parameters 1 Encode Period 1 @ 80 MSPS tENC Full V 12.5 ns Encode Pulsewidth High 2 @ 80 MSPS tENCH Full V 6.25 ns Encode Pulsewidth Low @ 80 MSPS tENCL Full V 6.25 ns ENCODE/DataReady Encode Rising to DataReady Falling tDR Full V 1.0 2.0 3.1 ns Encode Rising to DataReady Rising tE_DR Full V tENCH + tDR ns @ 80 MSPS (50% Duty Cycle) Full V 7.3 8.3 9.4 ns ENCODE/DATA (D13:0), OVR ENC to DATA Falling Low tE_FL Full V 2.4 4.7 7.0 ns ENC to DATA Rising Low tE_RL Full V 1.4 3.0 4.7 ns ENCODE to DATA Delay (Hold Time)3 tH_E Full V 1.4 3.0 4.7 ns ENCODE to DATA Delay (Setup Time) 4 tS_E Full V tENC – tE_FL ns Encode = 80 MSPS (50% Duty Cycle) Full V 5.3 7.6 10.0 ns DataReady (DRY 5)/DATA, OVR DataReady to DATA Delay (Hold Time) 2 tH_DR Full V Note 6 ns Encode = 80 MSPS (50% Duty Cycle) 6.6 7.2 7.9 DataReady to DATA Delay (Setup Time) 2 tS_DR Full V Note 6 ns Encode = 80 MSPS (50% Duty Cycle) 2.1 3.6 5.1 APERTURE DELAY tA 25 ∞CV –500 ps APERTURE UNCERTAINTY (Jitter) tJ 25 ∞CV 0.1 ps rms NOTES 1Several timing parameters are a function of t ENC and tENCH. 2To compensate for a change in duty cycle for t H_DR and tS_DR use the following equation: NewtH_DR = (tH_DR – % Change(tENCH)) NewtS_DR = (tS_DR – % Change(tENCH)) 3ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the Analog-to-Digital Converter, t E_RL = tH_E. 4ENCODE TO DATA Delay (Setup Time) is calculated relative to 80 MSPS (50% duty cycle). To calculate t S_E for a given encode, use the following equation: NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: NewtS_E(TYP) = 25 ¥ 10–9 – 15.38 ¥ 10–9 + 9.8 ¥ 10–9 = 19.4 ¥ 10 –9). 5DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 6DataReady to DATA Delay (t H_DR and tS_DR) is calculated relative to 80 MSPS (50% duty cycle) and is dependent on t ENC and duty cycle. To calculate tH_DR and tS_DR for a given encode, use the following equations: NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: NewtH_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 7.2 ¥ 10–9 = 13.45 ¥ 10–9 NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 3.6 ¥ 10–9 = 9.85 ¥ 10–9 Specifications subject to change without notice. tS_DR tA AIN N N+1 N+2 N+3 N+4 tENC tENCH tENCL tE_FL tE_RL tE_DR tS_E tH_E tDR tH_DR NN+1 N+2 N+3 N+4 N N–1 N–2 N–3 ENC, ENC D[13:0], OVR DRY Figure 1. Timing Diagram (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40 C, TMAX = +85 C, CLOAD = 10 pF, unless otherwise noted.) |
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