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MPC8280CVVBX Arkusz danych(PDF) 30 Page - NXP Semiconductors |
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MPC8280CVVBX Arkusz danych(HTML) 30 Page - NXP Semiconductors |
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30 / 83 page ![]() MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2 30 Freescale Semiconductor Clock Configuration Modes 7.2 PCI Host Mode These tables show clock configurations for PCI host mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the following: NOTE: PCI_MODCK In PCI mode only, PCI_MODCK comes from the LGPL5 pin and MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}. NOTE: Tval (Output Hold) The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing. 1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev0.1 the minimum CPU frequency is 250 MHz; for Rev A or later the minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. 2 MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins. 3 60x and local bus frequency. Identical to CLKIN. 4 CPM multiplication factor = CPM clock/bus clock 5 CPU multiplication factor = Core PLL multiplication factor Table 19. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1,2 Mode3 Bus Clock4 (MHz) CPM Multiplication Factor5 CPM Clock (MHz) CPU Multiplication Factor6 CPU Clock (MHz) PCI Division Factor PCI Clock (MHz) MODCK_H- MODCK[1-3] Low High Low High Low High Low High Default Modes (MODCK_H=0000) 0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0000_011 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7 0000_100 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7 0000_101 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0000_110 50.0 66.7 3.5 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7 0000_111 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 Full Configuration Modes 0001_000 50.0 66.7 3 150.0 200.0 5 250.0 333.3 3 50.0 66.7 |
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