MPC8280CVRMX datasheet(80/83 Pages) NXP

80 / 83 page

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

Document Revision History

1.4

11/2005

• In Section 6.2, “SIU AC Characteristics”, modified the note on CLKIN Jitter and Duty Cycle.

• Modified Figure 17 to display all text.

1.3

01/2005

• Modification for correct display of assertion level (“overbar”) for some signals

1.2

12/2004

• Section 2: removed voltage tracking note

• Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset

• Table 5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external

pullup removed.

• Table 5: Note 4 added regarding IIC compatibility

• Section 4.2: New information about jumper-to-case thermal resistance

• Section 4.3: New information about jumper-to-board thermal resistance

• Section 4.4: New information about estimation with simulation

• Section 4.6: Updated description of layout practices

• Section 6: Added sentence providing derating factor

•Section 6.1, “CPM AC Characteristics”: added Note: Rise/Fall Time on CPM Input Pins

• Table 9: updated values for following specs: sp42, sp43, sp42a

• Table 20: updated values for following specs: sp16b, sp18b, sp20, sp22

• Section 6.2: added spread sprectrum clocking note

• Table 11: combined specs sp11 and sp11a

• Sections 7.2, 7.3: unit of ns added to Tval notes

• Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin

of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

Table 27. Document Revision History (continued)

Revision

Date

Substantive Changes

MPC8280CVRMX Arkusz danych(PDF) 80 Page - NXP Semiconductors