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ST72334J Arkusz danych(PDF) 29 Page - STMicroelectronics |
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ST72334J Arkusz danych(HTML) 29 Page - STMicroelectronics |
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29 / 125 page ![]() ST72334J/N, ST72314J/N, ST72124J 29/125 RESET SEQUENCE MANAGER (Cont’d) Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 18. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tDELAYmin. Figure 18. Watchdog RESET Sequence RESET RUN DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR RUN RESET PIN EXTERNAL RESET SOURCE VDD VLVDf VDDnominal WATCHDOG RESET WATCHDOG UNDERFLOW tDELAYmin |
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