HC705JB2GRSSLASHH datasheet(47/128 Pages) NXP

Numer części	HC705JB2GRS/H

Szczegółowy opis	Industry standard M68HC05 CPU core

PDF	128 Pages

Scroll/Zoom	100%

Producent	NXP [NXP Semiconductors]

Strona internetowa	http://www.nxp.com

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47 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

INPUT/OUTPUT PORTS

REV 1.1

7-1

SECTION 7

INPUT/OUTPUT PORTS

In the Normal Operating Mode, there are 11 bidirectional I/O lines arranged as

one 8-bit I/O port (Port A), and one 3-bit I/O port (Port B). Each port line can be

programed as either input or output, under software control, by the data direction

registers (DDR’s). Also, if enabled by a mask option, all Port A and Port B I/O pins

may have individual software programmable pulldown or pullup devices. PA4 to

PA7 and PB1 & PB2 pins have the additional properties of sinking higher current.

PA0 to PA3 may function as additional IRQ interrupt input sources (mask option).

PB1 and PB2 have open drain output drivers, with optional slow falling-edge

output transitions. The transition delay is 170ns (typical), with a bus rate of 3MHz

and a loading of 50pF.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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