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STFPC311 Arkusz danych(PDF) 9 Page - STMicroelectronics |
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STFPC311 Arkusz danych(HTML) 9 Page - STMicroelectronics |
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9 / 39 page ![]() STFPC311 3 Initialization 9/39 3.6.1 Watchdog timer operation during power-up Figure 3. Power-up condition Note: Watchdog timer is turned off by default upon READY assertion. If Watchdog is to be kept on during READY high condition, the WDG registers must be set accordingly by proper commands through SPI bus. In this power-up condition, the watchdog timer is triggered by internal POR pulse. During power-up, the watchdog timer value is 10s. |
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