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STM32C011F6U6TR Arkusz danych(PDF) 77 Page - STMicroelectronics

Numer części STM32C011F6U6TR
Szczegółowy opis  Arm® Cortex®-M0 32-bit MCU, 32 KB Flash, 6 KB RAM,2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V
PDF  94 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32C011F6U6TR Arkusz danych(HTML) 77 Page - STMicroelectronics

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DS13866 Rev 3
77/94
STM32C011x4/x6
Electrical characteristics
79
Figure 25. I2S slave timing diagram (Philips protocol)
Table 62. I2S characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S main clock output
-
-
48
MHz
fCK
I2S clock frequency
Master TX
-
12
MHz
Master RX
-
12
Slave TX
-
15
Slave RX
-
48
tv(WS)
WS valid time
Master mode
-
5
ns
th(WS)
WS hold time
Master mode
2
-
tsu(WS)
WS setup time
Slave mode
3.5
-
th(WS)
WS hold time
Slave mode
1
-
tsu(SD_MR)
Data input setup time
Master receiver
5
-
tsu(SD_SR)
Slave receiver
2.5
-
th(SD_MR)
Data input hold time
Master receiver
1.5
-
ns
th(SD_SR)
Slave receiver
1
-
tv(SD_ST)
Data output valid time
Slave transmitter (after enable edge)
-
19,5
tv(SD_MT)
Master transmitter (after enable edge)
-
5
th(SD_ST)
Data output hold time
Slave transmitter (after enable edge)
8
-
th(SD_MT)
Master transmitter (after enable edge)
2.5
-
1. Evaluated by characterization – Not tested in production.
MSv39721V1
CPOL = 0
CPOL = 1
tc(CK)
WS input
SDtransmit
SDreceive
tw(CKH)
tw(CKL)
tsu(WS)
tv(SD_ST)
th(SD_ST)
th(WS)
tsu(SD_SR)
th(SD_SR)
MSB receive
Bitn receive
LSB receive
MSB transmit
Bitn transmit
LSB receive(2)
LSB transmit(2)



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