9P960

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

IDT® DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

5

9P960

REV A 051811

DDRIII Specifications

Recommended Operating Conditions

Electrical Characteristics–Input/Supply/Common Output Parameters

Timing

TA = 0 - 70°C; Supply Voltage AVDD = 1.8V+/- 0.1V, VDD = 1.5 V +/- 5% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

VDD1.8/1.5

1.425

1.5

1.575

V

A

VDD1 .8

1.7

1.8

1.9

V

Low level input voltage

VIL

CLK_INT, CLK_IN C, FB_IN

0.35VDD

V

High level input voltage

VIH

CLK_INT, CLK_IN C, FB_IN

0.65VDD

V

Operating free-air

temperature

T

A

070

°C

Notes:

1. Unused inputs must be held high or low to prevent them from floating.

Supply Voltage

TA = 0 - 70°C; Supply Voltage AVDD = 1.8V+/- 0.1V, VDD = 1.5 V +/- 5% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input High Current

IIH

VI = VDD or GND

10

µA

Input Low Current

I

IL

V

I = VDD or GND

-10

µA

Output Disabled Low

Current

IODL

OE = L, VODL = 100mV

100

µA

IDDA

AVDD1.8 @ 400MHz

34

45

mA

I

DD 1.5

VDD1.8/1.5 @ 400MHz

331

375

mA

IDDLD

CL = 0pf

500

µA

Input Clamp Current

V

IK

V

I < 0 o r V I > VDD

-50

mA

Differential output clock

sw ing

V

OD

I

OH = -11mA

500

VDD1.8/1.5

mV

Input Capacitance

1

C

IN

VI = GND or VDD

25

pF

Output Capacitance

1

C

OUT

VOUT = GND or VDD

25

pF

Operating Supply Current

TA = 0 - 70°C; Supply Voltage AVDD = 1.8V+/- 0.1V, VDD = 1.5 V +/- 5% (unless otherwise stated)

PARAMETER

SYMBOL

CON DITIONS

MIN

TYP

MAX

UNITS

Max clock frequency

freqop

1.5V+5% @ 25°C

300

700

MH z

Application Frequency

Range

freq

App

1.5V+5% @ 25°C

300

670

MH z

Input clock duty cycle

d

tin

40

60

%

CLK stabilization

T

STAB

15

µs