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AT25DF041B Arkusz danych(PDF) 10 Page - Renesas Technology Corp |
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AT25DF041B Arkusz danych(HTML) 10 Page - Renesas Technology Corp |
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10 / 64 page ![]() DS-AT25DF041B-040 Rev. H Page 10 12/13/22 © 2022 Renesas Electronics AT25DF041B Datasheet 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF041B can be erased in three levels of granularity: sectors, blocks and pages. There is also a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. The erase operations can be performed at the chip, sector, block, or page level. Program operations to the device can be done at the full page level or at the byte level (a variable number of bytes, from 1byte to 256 bytes per page). Figure 5 shows each erase level. Figure 5. Memory Architecture Diagram |
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