2

Pin connection and functions

Figure 3. Pin connection (top view)

Table 1. Pin description

No.

Name

Function

1

VCC

Supply voltage. The internal high voltage start-up generator charges an electrolytic capacitor connected

between this pin and GND as long as the voltage on the pin is below the start-up threshold of the IC,

after it is disabled and the chip turns on. A bypass capacitor to GND has to be placed close to the pins

to get a clean bias voltage.

2

GD

Gate driver output. The output stage is able to drive power MOSFETs and IGBTs; it is capable of 0.7 A

source current and 1.5 A sink current (typical values).

3

GND

IC ground. Current return for both the signal/bias part of the IC and the gate driver current. All of

the ground connections of the bias components should be tied to a track going to this pin and kept

separate from any pulsed current return.

4

CS

Current sense input. The inductor current is sensed through a resistor RS on the current return side.

The resulting negative voltage is applied to this pin and compared to an internal sinusoidal-shaped

reference to determine the turn-off instant of the external power switch. The pin is equipped with an

internal current generator (sourced current during power switch on-time); it can be used, by simply

adding a series resistor (RTHD_CCM) for improved THD in CCM operation.

If the voltage on the pin goes below VCS_OCP1 (-0.49 V typ.) the internal overcurrent comparator is

triggered and terminates the conduction cycle of the external power switch before the normal PWM

circuit does. In this way, the peak inductor current is limited at a maximum of 0.49/RS.

A second overcurrent level set at VCS_OCP2 (-0.75 V typ.) detects abnormal current values (e.g. due to

boost inductor saturation) and, on this occurrence, activates a safety procedure that immediately stops

the converter activity until the current level reaches the zero-current threshold VCS_ZCD (-10 mV typical

value). It allows safe operations also during current surges occurring at power-up or after a mains dip

or missing cycle; in fact it allows switching start/restart only when the overcurrent event is definitively

over.

5

FB

Inverting input of the trans-conductance Error Amplifier (OTA).

The information on the output voltage of the PFC regulator is fed into the pin through a resistor divider

so that its voltage is proportional to the instantaneous value of the high voltage bus (VBULK). Under

steady-state conditions the voltage on pin sits at the internal reference of the error amplifier (VREF =

2.5 V). If the voltage exceeds the steady-state value by 7% (VFB > VFB_S), e.g. due to an output voltage

overshoot, the switching activity is stopped until VFB < VFB_R (2.55V typ.).

If the voltage at the FB pin is below VFB_FF/EBM (0.5 V typ.) either a failure of the output divider is

assumed or the device is externally forced in burst-mode operation. In both cases the PFC controller

is stopped with low consumption. See Section 5.7 Idle operation (external burst-mode function) and

Section 5.9.6 Feedback failure detection for further details.

L4985

Pin connection and functions

DS13769 - Rev 3

page 4/27