Rev C 3/20/15

4

LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER

83115 DATA SHEET

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

NOTE 1: Outputs terminated with 50

 to V

DD/2. See Parameter Measurement Information, Output Load Test Circuit diagram.

AC Electrical Characteristics

Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at VDD/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

VIH

Input High Voltage

OE0:OE2

2

VDD + 0.3

V

IN

2

VDD + 0.3

V

VIL

Input Low Voltage

OE0:OE2

-0.3

0.8

V

IN

-0.3

1.3

V

IIH

Input High Current

OE0:OE2

VDD = VIN = 3.465V

5

µA

IN

VDD = VIN = 3.465V

150

µA

IIL

Input Low Current

OE0:OE2

VDD = 3.465V, VIN = 0V

-150

µA

IN

VDD = 3.465V, VIN = 0V

-5

µA

VOH

Output High Voltage; NOTE 1

VDD = 3.3V ± 5%

2.6

V

VOL

Output Low Voltage; NOTE 1

VDD = 3.3V ± 5%

0.5

V

IOZL

Output Hi-Z Current Low

5µA

IOZH

Output Hi-Z Current High

5µA

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

200

MHz

tjit(

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

Integration Range:

12kHz – 20MHz

0.09

ps

tpLH

Propagation Delay; NOTE 1

ƒ

 200MHz

1.7

2.4

3.1

ns

tsk(o)

Output Skew; NOTE 2, 4

Measured on the Rising Edge

@ VDD/2

150

250

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

Measured on the Rising Edge

@ VDD/2

800

ps

tR / tF

Output Rise/Fall Time4

20% to 80%

400

800

ps

odc

Output Duty Cycle

45

55

%

tEN

Output Enable Time

20

ns

tDIS

Output Disable Time

20

ns