P83C528FBA datasheet(13/26 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C528/83C528

CMOS single-chip 8-bit microcontrollers

1995 Feb 02

DC ELECTRICAL CHARACTERISTICS (Continued)

Tamb = 0°C to +70°C (VDD = 5V ±20%), –40°C to +85°C (VDD = 5V ±20%), or –40°C to +125°C (VDD = 5V ±10%), VSS=0V

TEST

LIMITS

SYMBOL

PARAMETER

PART TYPE

CONDITIONS

MIN

MAX

UNIT

IIL1

Input leakage current, port 0, EA

0.45<Vi<VDD

±10

µA

IIL2

Input leakage current, P1.6/SCL, P1.7/SDA

0V<Vi<6.0V

0V<VDD<6.0V

±10

µA

IDD

Power supply current:

See notes 6, 7

Active mode

Idle mode

Power down mode

–40

°C to +125°C

100

150

µA

RRST

Internal reset pull-down resistor

150

Ω

CIO

Capacitance of I/O buffer

Freq.=1MHz

Tamb = 25°C

NOTES:

1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level ouput voltage of ALE, Port

1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0

transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such

cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

2. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD

specification when the address bits are stabilizing.

3. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so a voltage below 0.3VDD will be recognized as a logic 0

while an input above 0.7VDD will be recognized as a logic 1.

4. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:

10mA

Maximum IOL per 8–bit port: –

Port 0:

26mA

Ports 1, 2, & 3:

15mA

Maximum total IOL for all output pins:

71mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

5. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when VIN is approximately 2V.

6. See Figures 9 through 12 for IDD test conditions.

7. IDDMAX at other frequencies can be derived from the figure below, where FREQ is the external oscillator frequency in MHz.

IDDMAX is given in mA.

MAX ACTIVE MODE

TYP ACTIVE MODE

MAX IDLE MODE

TYP IDLE MODE

IDD vs. FREQUENCY

FREQ. AT XTAL1 (MHz)

VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF DEVICE UNDER TEST.

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