FS6407 datasheet(39/111 Pages) NXP

Numer części	FS6407

Szczegółowy opis	Power system basis chip with high speed can transceiver

PDF	111 Pages

Scroll/Zoom	100%

Producent	NXP [NXP Semiconductors]

Strona internetowa	http://www.nxp.com

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39 / 111 page

NXP Semiconductors

FS6407/FS6408

6.5.3.1

RST error counter at start-up or resuming from LPOFF mode

At start-up or when resuming from LPOFF mode the reset error counter starts at level 1 and FS0B is asserted low. To remove the

activation of FS0B, the RST error counter must go back to value “0” (seven consecutive good watchdog refresh decreases the reset error

counter down to 0) and a right command is sent to FS_OUT register (Figure 20).

Figure 18. Example of WD operation generating a reset (WD_error_cnt = 6)

Figure 19. Example of WD operation leading a decrement of the reset error counter (WD_resfresh_cnt = 6)

WD window

NOK

WD error

counter

NOK

Reset error

counter

RSTB

WD Refresh

counter

RSTb

delay time

1st WD refresh OK after

INIT phase. Start of the

WD window

New fully OPEN window of

256 ms

WD window

WD error

counter

Reset error

counter

RSTb

WD Refresh

counter

RSTb

delay time

NOK

New fully OPEN window of

256 ms

FS6407 Arkusz danych(PDF) 39 Page - NXP Semiconductors