AD9980

Preliminary Technical Data

Rev. 0 | Page 22 of 44

TWO-WIRE SERIAL REGISTER MAP

The AD9980 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to

write and read the control registers through the two-wire serial interface port.

Table 12. Control Register Map

Hexadecimal

Address

Read and

Write or

Read Only

Bits

Default

Value

Register

Name

Description

0x00

RO

7:0

Chip Revision

An 8-bit register that represents the silicon revision level.

0x01

R/W

7:0

0110 1001

PLL Div MSB

This register is for Bits [11:4] of the PLL divider. Larger values mean

the PLL operates at a faster rate. This register should be loaded first

whenever a change is needed. (This will give the PLL more time to

lock).1

0x02

R/W

7:4

1101 ****

PLL Div LSB

Bits [7:4] LSBs of the PLL divider word. Links to the PLL Div MSB to

make a 12-bit register.

1

0x03

R/W

7:6

01** ****

VCO/CPMP

Bits [7:6] VCO Range. Selects VCO frequency range.

(See PLL description).

5:3

**00 1***

Bits [5:3] Charge Pump Current. Varies the current that drives the

low-pass filter. (See PLL description).

2

**** *0**

Bit 2. External Clock Enable

0x04

R/W

7:3

1000 0***

Phase Adjust

ADC clock phase adjustment. Larger values mean more delay.

(1 LSB = T/32).

0x05

R/W

6:0

*100 0000

Red Gain MSB

7-Bit Red Channel Gain Control. Controls the ADC input range

(contrast) of each respective channel. Bigger values give less

contrast.2

0x06

R/W

7:0

0000 0000

Must be written to 0x00 following a write of Register 0x05 for

proper operation.

0x07

R/W

6:0

*100 0000

Green Gain

MSB

7-Bit Green Channel Gain Control. Controls the ADC input range

(contrast) of each respective channel. Bigger values give less

contrast.

2

0x08

R/W

7:0

0000 0000

Must be written to 0x00 following a write of Register 0x07 for

proper operation.

0x09

R/W

6:0

*100 0000

Blue Gain MSB

7-Bit Blue Channel Gain Control. Controls the ADC input range

(contrast) of each respective channel. Bigger values give less

contrast.

2

0x0A

R/W

7:0

0000 0000

Must be written to 0x00 following a write of Register 0x09 for

proper operation.

0x0B

R/W

7:0

0100 0000

Red Offset MSB

8-Bit MSB of the Red Channel Offset Control. Controls the dc offset

(brightness) of each respective channel. Bigger values decrease

brightness.

1

0x0C

R/W

7

0*** ****

Red Offset

Linked with 0x0B to form the 9-bit red offset that controls the dc

offset (brightness) of the red channel in auto-offset mode.

0x0D

R/W

7:0

0100 0000

Green Offset

MSB

8-Bit MSB of the Green Channel Offset Control. Controls the dc

offset (brightness) of each respective channel. Bigger values

decrease brightness.

1

0x0E

R/W

7

0*** ****

Green Offset

Linked with 0x0D to form the 9-bit green offset that controls the

dc offset (brightness) of the green channel in auto-offset mode.

0x0F

R/W

7:0

0100 0000

Blue Offset

MSB

8-Bit MSB of the Red Channel Offset Control. Controls the dc offset

(brightness) of each respective channel. Bigger values decrease

brightness.

1

0x10

R/W

7

0*** ****

Blue Offset

Linked with 0x0F to form the 9-bit blue offset that controls the dc

offset (brightness) of the blue channel in auto-offset mode.

0x11

R/W

7:0

0010 0000

Sync Separator

Threshold

This register sets the threshold of the sync separator’s digital

comparator.