HC705MC4GRSSLASHD datasheet(50/180 Pages) NXP

Numer części	HC705MC4GRS/D

Szczegółowy opis	General Release Specification

PDF	180 Pages

Scroll/Zoom	100%

Producent	NXP [NXP Semiconductors]

Strona internetowa	http://www.nxp.com

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50 / 180 page

Resets

MC68HC705MC4 — Rev. 2.0

Resets

Figure 5-1. Reset Block Diagram

5.3 External Reset

The RESET input is the only external reset and is connected to an

internal Schmitt trigger. The external reset occurs whenever the RESET

input is driven below the lower threshold and remains in reset until the

RESET pin rises above the upper threshold. The upper and lower

thresholds are given in Section 14. Electrical Specifications.

5.4 Internal Resets

The three internally generated resets are the illegal address, the initial

power-on reset (POR) function, and the computer operating properly

(COP) watchdog timer function.

RESET

RST

POWER-ON

RESET

(POR)

RESET

COP

WATCHDOG

(COPR)

VDD

OSC

DATA

ADDRESS

LATCH

TO CPU AND

PERIPHERALS

INTERNAL CLOCK

INSTRUCTION

LOAD CLOCK

ADDRESS

ILLEGAL

ADDRESS

4-CYCLE

COUNTER

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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