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ISL81601 Arkusz danych(PDF) 7 Page - Renesas Technology Corp |
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ISL81601 Arkusz danych(HTML) 7 Page - Renesas Technology Corp |
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7 / 54 page ![]() FN9299 Rev.3.1 Page 7 of 53 May 27, 2021 ISL81601 1. Overview 1.2 Block Diagram Figure 6. Block Diagram POR Enable Bias Supplies Reference Fault Latch OVP HICCUPOCP FB_OUT PGOOD EN/UVLO VIN VDD EXTBIAS FB_OUT SS/TRK CS+ 2µA SS/TRK SS/TRK + _ + _ 0.8V REF Slope-Comp Ramp Generator Clock RT SYNC EPAD PWM VOUT VIN IMON_OUT VCC5V LDO LDO LDO VDD BOOT1 UG1 PHASE1 LG1 PWM_MODE PGND Adaptive Dead Time Boot Refresh Logic VDD BOOT2 UG2 PHASE2 LG2 OC_MODE PGND Adaptive Dead Time Boot Refresh Logic GM1 COMP CS- A1 Slope Compensation Buck-Boost Logic PWM Logic DEM Burst Logic PWM Comparator + _ COMP COMP ISEN+ ISEN- A2 + _ VOUT + _ PWM Buck PWM Boost FB_IN CLKOUT DITHER + _ + _ 0.8V REF GM2 1.2V GM3 GM4 IMON_IN PLL_COMP SGND OV OV BSTEN CLKEN BSTEN CLKEN BSTEN CLKEN OV Pulse-by-Pulse Negative Peak Current Limit PGND + _ Pulse-by-Pulse Peak Current Limit 1.2V |
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