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Data Sheet
RSC-4128
39
P/N 80-0206-R
© 2006 Sensory Inc.
Address R/W
Name
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0000 0000
pwrl
detect
thrh2
thrh1
thrh0
thrl2
thrl1
thrl0
CD
W
RESERVED
R
RESERVED
CC
RESERVED
CB
RESERVED
CA
RESERVED
C9
RESERVED
C8
RESERVED
RESERVED
C7
RESERVED
C6
RESERVED
C5
RESERVED
C4
RESERVED
C3
RESERVED
RESERVED
C2
RESERVED
RESERVED
C1
RESERVED
RESERVED
C0
RESERVED
RESERVED
Reset: “x” = unknown/don’t care, ‘-‘ = not implemented
* Only “0” can be written to “irq” bits. “1” is a “nop” for the bit to which it is written. When using FluentChip™ technology, always write “1” to
“block” and “endmark” in the “irq” register to avoid conflicting with technology code control of these bits.
** Write value is ignored and reload register value is written instead.
*** -anctlen (Bit7) of values written to the “anCtl” register must be “0” to enable writing the other bits in the value to “anCtl”.
**** When using FluentChip™ technology, “fclk_on”, “L1clk_on”, and “block” and “endmark” in the “imr” register should be left at the values
programmed by the technology code. A read-modify-write action should be used to modify the registers to avoid changing these bits.
***** “trap” must always be written as “0” in the “flags” and “flagsHold” registers
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