CS5320 datasheet(86/160 Pages) AMCC

86 / 160 page

S5320 – PCI Match Maker: Initialization

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

transfer was successful or not. If XFER_FAIL is

asserted, this indicates that a transfer to the

nvRAM did not receive an ACKNOWLEDGE. The

read data in RCR(32:16) should not be consid-

ered valid. This flag remains set until the start of

the next read/write operation.

PCI BUS CONFIGURATION CYCLES

Cycles beginning with the assertion IDSEL and

FRAME# along with the two configuration command

states for C/BE[3:0] (configuration read or write)

access the selected device’s configuration space. Dur-

ing the address phase of the configuration cycle just

described, the values of AD0 and AD1 identify if the

access is a Type 0 configuration cycle or a Type 1 con-

figuration cycle. Type 0 cycles have AD0 and AD1

equal to 0 and are used to access PCI bus agents.

Type 1 configuration cycles are intended only for

bridge devices and have AD0 as a 1 with AD1 as a 0

during the address phase.

The S5320 PCI device is a bus agent (not a bridge)

and responds only to a Type 0 configuration accesses.

Figure 41 depicts the state of the AD bus during the

address phase of a Type 0 configuration access. The

S5320 controller does not support the multiple function

numbers field (AD[10:8]) and only responds to the all-0

function number value.

Figure 41. PCI AD Bus Definition Type 0 Configuration Access

The configuration registers for the S5320 PCI control-

ler can only be accessed under the following

conditions:

•

IDSEL high (PCI slot unique signal which iden-

tifies access to configuration registers) along

with FRAME# low.

•

Address bits A0 and A1 are 0 (Identifies a Type

0 configuration access).

•

Address bits A8, A9, and A10 are 0 (Function

number field of 0 supported).

•

Command bits, C/BE[3:0]# must identify a con-

figuration cycle command (101X).

Figure 42 describes the signal timing relationships for

configuration read cycles. Figure 43 describes config-

uration write cycles.

Figure 42. Type 0 Configuration Read Cycles

00h

TYPE 0

000

NUMBER

XXXXXXXX - INTERNAL REGISTER

ADDRESS

(DEVICE ID, ETC.)

FUNCTION

NUMBER

RESERVED

PCI CLK

FRAME#

AD[31:0]

C/BE[3:0]#

IRDY#

T RDY#

IDSEL

DEVSEL#

ADD

DAT A

1010

BYT E EN

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