ICS558-01

PECL/CMOS TO CMOS CLOCK DRIVER

PECL CLOCK DRIVER

IDT™ / ICS™ PECL/CMOS TO CMOS CLOCK DRIVER

2

ICS558-01

REV F 051310

Pin Assignment

Input Clock Selection

Tri-State Table

Output Divide Selection

Pin Descriptions

12

1

11

2

10

3

9

S0

4

S1

5

VDDP

6

VDDC

7

PECLIN

8

PECLIN

CLK1

CLK2

CLK3

GND

CLK4

OE1

CMOSIN

GND

16

15

14

13

OE0

SELPECL

16-pin 173 Mil (0.65mm) TSSOP

SELPECL

Input

0CMOSIN

1

PECLIN

OE1 OE0

CLK 1

CLK 2, 3, 4

0

0

Tri-state

Tri-state

0

1

Clock ON

Tri-state

1

0

Tri-state

Clock ON

1

1

Clock ON

Clock ON

S1

S0

Output Divide

00

/1

01

/2

10

/3

11

/4

Pin

Number

Pin

Name

Pin Type

Pin Description

1

S0

Input

Select 0 for output divider. See table above. Internal pull-up to VDDP.

2

S1

Input

Select 1 for output divider. See table above. Internal pull-up to VDDP.

3

VDDP

Power

Connect to +3.3 V or +5 V. Decouple to pin 6.

4

PECLIN

Clock Input

PECL input. Connect to ground if not used.

5

PECLIN

Clock Input

Complimentary PECL input. Connect to ground if not used.

6

GND

Power

Connect to ground.

7

CMOSIN

Clock Input

CMOS input. Connect to ground if not used.

8

OE0

Input

Output Enable 0. See table above. Internal pull-up to VDDP.

9

OE1

Input

Output Enable 1. See table above. Internal pull-up to VDDP.

10

GND

Power

Connect to ground.

11

CLK4

Output

Low skew clock output.

12

CLK3

Output

Low skew clock output.

13

CLK2

Output

Low skew clock output.

14

CLK1

Output

Low skew clock output.

15

VDDC

Power

Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10.

16

SELPECL

Input

Selects PECL or CMOS input. See table above. Internal pull-up to

VDDP.