ICS1524AMLF datasheet(2/25 Pages) RENESAS

Numer części	ICS1524AMLF

Szczegółowy opis	Dual Output Phase Controlled SSTL_3/PECL Clock Generator

PDF	25 Pages

Scroll/Zoom	100%

Producent	RENESAS [Renesas Technology Corp]

Strona internetowa	http://www.renesas.com

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2 / 25 page

ICS1524A

Document Revision History

Rev A

ICS1523 Rev T Datasheet used as a starting template

New Block Diagram substituted for old 1523 one

Removed reference to CLK / 2 Functionality

Created a set of clock outputs that bypass the DPA

External PDEN is now the IN-SEL MUX control bit

Text descriptions changed to support new 1524 block diagram

Rev B

Replaced page 15 “Layout Guidelines”

Replaced SIOC Package diagram on page 22

“Advanced Status” removed

Redrew front page graphics for clairity

Rev C

Corrected Chip Revision and Chip Version values on page 5

Changed Title on Page 1

Minor format changes to pages 8 and 21

Corrected pin names on page 10

Rev D

Miscellaneous updates to Block Diagram on page 3

Changed reference from “Phase Detector” to “Charge Pump”. Pages 4-7, 10

ICS1524AMLF Arkusz danych(PDF) 2 Page - Renesas Technology Corp