7

ICS1574B

]

3

[

K

L

C

P]

2

[

K

L

C

P]

1

[

K

L

C

P]

0

[

K

L

C

PS

U

L

U

D

O

M

0000

3

000

1

)

a

(

4

00

1

0

)

b

(

4

00

11

5

01

0

0

6

01

01

)

a

(

8

01

1

0

)

b

(

8

0

111

0

1

1X

0

0

2

1

1X

0

1

)

a

(

6

1

1X

1

0

)

b

(

6

1

1X

1

1

0

2

]

1

[

S]

0

[

SN

O

I

T

P

I

R

C

S

E

D

00

K

L

C

P

e

h

t

f

o

t

u

p

t

u

o

e

h

T

.

)

L

L

P

(

F

=

)

K

L

C

(

F

.

1

=

r

e

l

a

c

s

-

t

s

o

P

.

t

u

p

t

u

o

K

L

C

P

e

h

t

s

e

v

i

r

d

r

e

d

i

v

i

d

01

e

h

t

f

o

t

u

p

t

u

o

e

h

T

.

2

/

)

L

L

P

(

F

=

)

K

L

C

(

F

.

2

=

r

e

l

a

c

s

-

t

s

o

P

.

t

u

p

t

u

o

K

L

C

P

e

h

t

s

e

v

i

r

d

r

e

d

i

v

i

d

K

L

C

P

10

e

h

t

f

o

t

u

p

t

u

o

e

h

T

.

4

/

)

L

L

P

(

F

=

)

K

L

C

(

F

.

4

=

r

e

l

a

c

s

-

t

s

o

P

.

t

u

p

t

u

o

K

L

C

P

e

h

t

s

e

v

i

r

d

r

e

d

i

v

i

d

K

L

C

P

11

L

C

P

_

X

U

A

e

h

T

.

E

D

O

M

T

S

E

T

N

E

-

X

U

A

K

e

h

t

s

e

v

i

r

d

t

i

b

.

t

u

p

t

u

o

K

L

C

P

Register Mapping — ICS1574B

NOTE: It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to

automatically generate all register values based on requirements. Contact factory for details.

BIT(S)

BIT REF.

DESCRIPTION

1 – 4

PCLK[0]..PCLK[3]

Sets PCLK divider modulus according to this table.

These bits are set to implement a divide-by-four on power-up.

(X = Don't Care)

5, 6

Reserved

Must be set to 0.

7

Reserved

Must be set to 1.

8

SELXTAL

Normally set to 0. When set to logic 1, passes the reference

frequency to the post-scaler instead of the PLL output

(defaults to 1 on power-up).

9

Reserved

Must be set to 0.

10

Reserved

Must be set to 1.

11, 12

Reserved

Must be set to 0.

13 – 14

S[0]..S[1]

PLL post-scaler / test mode select bits.