17

ICS950805

0649H—02/25/05

When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks

must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with

a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description

is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.

Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more

than one clock cycle to complete.

PD# - Assertion (transition from logic "1" to logic "0")

PD# Functionality

#

P

O

T

S

_

U

P

CT

U

P

CC

U

P

C6

6

V

3T

U

O

_

z

H

M

6

6

F

_

K

L

C

I

C

P

K

L

C

I

C

P

K

L

C

I

C

P

T

O

D

/

B

S

U

z

H

M

8

4

1l

a

m

r

o

Nl

a

m

r

o

Nz

H

M

6

6N

I

_

z

H

M

6

6N

I

_

z

H

M

6

6N

I

_

z

H

M

6

6z

H

M

8

4

0t

l

u

M

*

f

e

r

it

a

o

l

Fw

o

Lw

o

Lw

o

Lw

o

Lw

o

L

Power Down Assertion of Waveforms - Buffered Mode

0ns

PD#

CPUT 100MHz

CPUC 100MHz

3V66MHz

66MHz_IN

66MHz_OUT

PCI 33MHz

USB 48MHz

REF 14.318MHz

25ns

50ns