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Zakładka z wyszukiwarką danych komponentów |
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ICS951104 Arkusz danych(PDF) 1 Page - Renesas Technology Corp |
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ICS951104 Arkusz danych(HTML) 1 Page - Renesas Technology Corp |
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1 / 21 page  Integrated Circuit Systems, Inc. ICS951104 Preliminary Product Preview 0485G—10/13/05 Block Diagram Pin Configuration Recommended Application: ALI 1671/1672 P4 Chipset Output Features: • 2 - Pairs of differential CPU clocks (differential current mode) • 2 - AGP @ 3.3V • 7 - PCI @ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - REF @ 3.3V, 14.318MHz • 7 - Pairs of differential SSTL2 DDR @ 2.5V Features/Benefits: • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I 2C Index read/write and block read/write operations. • Uses external 14.318MHz crystal. Key Specifications: • CPU Output Jitter <150ps • AGP Output Jitter <250ps • DDR Output Jitter <250ps • CPU - DDR Skew <250ps • CPU - AGP/PCI Skew = 2.5ns ± 500ps Programmable Timing Control Hub TM for P4TM 56-Pin 300-mil SSOP, 240-mil TSSOP PLL2 PLL1 Spread Spectrum 48MHz REF0 PCICLK (5:0) AGP (1:0) X1 X2 XTAL OSC CPU DIVDER PCI DIVDER AGP DIVDER DDR DIVDER PD# MULTSEL SDATA SCLK Vtt_PWRGD CLK_STOP# PCI_STOP# FS (3:0) I REF RESET# Control Logic Config. Reg. 2 7 7 2 2 7 CPUCLKT (1:0) DDRC (6:0) CPUCLKC (1:0) DDRT (6:0) PCICLK_E Stop Stop Stop Stop Functionality Host Swing Select Functions 0 L E S I T L U M t e g r a T d r a o B Z m r e T / e c a r T , R e c n e r e f e R = f e r I V D D ) r R * 3 ( / t u p t u O t n e r r u C Z @ h o V 0s m h o 0 5 , % 1 1 2 2 = r R A m 0 0 . 5 = f e r I F E R I * 4 = h o I0 5 @ V 0 . 1 1s m h o 0 5 , % 1 5 7 4 = r R A m 2 3 . 2 = f e r I F E R I * 6 = h o I0 5 @ V 7 . 0 1 These outputs have 2x drive strength * Internal Pull-up resistor of 120K to VDD ** These inputs have 120K internal pull-down to GND FS3 FS2 FS1 FS0 CPU DDR AGP 0 0 0 0 66.66 66.66 66.66 0 0 0 1 66.66 100.00 66.66 0 0 1 0 100.00 66.66 66.66 0 0 1 1 100.00 100.00 66.66 0 1 0 0 100.00 133.33 66.66 0 1 0 1 133.33 66.66 66.66 0 1 1 0 133.33 100.00 66.66 0 1 1 1 133.33 133.33 66.66 1 0 0 0 66.66 66.66 66.66 1 0 0 1 66.66 100.00 66.66 1 0 1 0 100.00 66.66 66.66 1 0 1 1 100.00 100.00 66.66 1 1 0 0 100.00 133.33 66.66 1 1 0 1 133.33 66.66 66.66 1 1 1 0 133.33 100.00 66.66 1 1 1 1 133.33 133.33 66.66 AVCO_CORE X1 X2 GND VDD REF1 VDD GND FS1/PCICLK0 FS2/PCICLK9 SSEN_PCICLK1 PCICLK2 GND VDD PCICLK3 PCICLK4 PCICLK5 PCI_STOPB SDA FS3/AGP0 GND AGP1 AGP2 AGP3 CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 CLK_STOPB GND GND DDRT0 GND VDDL VDDL GND GND VDDL DDRC0 DDRT1 DDRC1 DDRT2 DDRC2 DDRT3 DDRC3 DDRT4 DDRC4 DDRT5 DDRC5 PWRGD_PDB SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 50M/REF_SEL_REF0 FS0_REF2 REF3_PLL_50 VDD |
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