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DFS04M Arkusz danych(PDF) 21 Page - STMicroelectronics |
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DFS04M Arkusz danych(HTML) 21 Page - STMicroelectronics |
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21 / 42 page ![]() 21/42 AN1262 APPLICATION NOTE Figure 8. Brownout protection circuit and timing diagram 15 CONTROL LOOP DESIGN The control loop can be summarized as shown in figure 9, where each block is described by its transfer function in the complex frequency domain represented by means of a Bode plot. Figure 9. Control loop Block Diagram The set PWM modulator + Power stage is what, in control theory terminology, is called the "plant", while the compensated error amplifier is the "controller". + - L6590A L6590D 2.5 V VinOK 50 µA Vin 6.4 V R1 R2 Vcc Vin VPKmin Vinmin VinOFF VinON VinOK Vcc PWM Vout OUTPUT DIVIDER + - Vref Vo COMPENSATED ERROR AMPLIFIER VCOMP PWM MODULATOR POWER STAGE G2(j ω) Vin D G1(j ω) |
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