ADM6819/ADM6820

Rev. 0 | Page 4 of 12

TIMING DIAGRAMS

Q1

GATE

LOGIC

SETV

EN

0.618V

0.618V

GND

R1

R2

R3

R4

ADM6819

FET

DRIVER

CHARGE

PUMP

UVLO

Figure 2. ADM6819 Solution for Validating Two Supplies Before Sequencing

10%

10%

90%

0.618V

(ADM6819 = 300ms,

ADM6820 = ADJ)

Figure 3. ADM6819/ADM6820 Timing Diagram Using SETV for Sequencing

10%

10%

90%

0.618V

0.618V

(300ms)

Figure 4. ADM6819 Timing Diagram Using EN and SETV for Sequencing