ADN2817 datasheet(27/35 Pages) AD

27 / 35 page

Preliminary Technical Data

ADN2817/ADN2818

Rev.Pr A | Page 27 of 35

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance, especially on Pin 23, which is the ground return for

the output buffers. The exposed pad should be connected to the

GND plane using plugged vias so that solder does not leak

through the vias during reflow.

Use of a 10 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they

should be placed between the IC power supply VCC and VEE,

as close as possible to the ADN2817/ADN2818 VCC pins.

If connections to the supply and ground are made through vias,

the use of multiple vias in parallel helps to reduce series

inductance, especially on Pin 24, which supplies power to the

high speed CLKOUTP/CLKOUTN and DATAOUTP/

DATAOUTN output buffers. Refer to the schematic in Figure

24 for recommended connections.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

( )

A/d

plane

where:

is the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm2).

d is the separation between planes (mm).

For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.

VCC

VEE

LOS

SDA

SCK

SAD D R5

VCC

VEE

AUT OM OD E

VCC

VREF

NIN

PI N

SL I CEP

SL ICEN

VEE

0.1

VCC

RTH

0.1

VCC

CL KOUT P

CL K OU T N

DATAOU T P

DATAOU T N

4x 100

transmission

lines

VCC

CIN

0.1

VCC

1n 0.1

VCC

0.47uF + 20%

>300M

Exposed Pad

Tied Off To

VEE Plane

With Vias

TIA

μC

insulation resistance

μC

I 2CController

Figure 24. Typical ADN2817/ADN2818 Applications Circuit

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