CS5501-SD datasheet(43/54 Pages) CIRRUS

43 / 54 page

RS-232 Port (for CS5501 only)

The CS5501 has a data output mode in which it

formats the data to be UART compatible; each

serial output byte is preceded by a start bit and

terminated with two stop bits. Serial data in this

format is commonly transferred using the RS-232

data interface. Therefore the evaluation board in-

cludes an RS-232 driver and output connector.

The CS5503 does not provide this output mode.

Micro Port

The CS5501/CS5503 was designed to be compat-

ible with many micro-controllers. Therefore the

evaluation board provides access to all of the data

outp ut p ins and th e co ntrol pins of the

CS5501/CS5503 on header connectors.

DIP Switch and CAL Pushbutton

Althoug h all of th e co ntrol lines to the

CS5501/CS5503 are available on header connec-

tors at the edge of the board, it is preferable to not

require software control of all of these pins.

Therefore DIP switch control is provided on some

of these control lines. The CAL input to the

CS5501/CS5503 is made available at a header pin

for remote control, but pushbutton control of CAL

is also provided.

Jumper Selections

The evaluation board has many jumper selectable

options. This table describes the jumper selections

available.

Selects between the on-board 4.9152 MHz

oscillator (INT) or an external (EXT) clock

source as the input to the clock generator/

divider chain.

Allows any of the counter/divider output

clock rates to be selected as the input clock

to the CS5501/CS5503.

Allows selection of baud rate clocks when

the CS5501 is in the UART compatible mode.

When using the on-board 4.9152 MHz stand-

ard baud rates between 1200 and 19,200 are

available.

Selects the divide ratio of the Decimation

Counter.

Selects one of the three available output data

modes of the CS5501 or one of two available

output data modes of the CS5503.

Enables the output of the Decimation

Counter to control the CS line of the

CS5501/CS5503.

P11

Connects the baud clock from the on-board

clock divider as the input to the SCLK pin

of the CS5501/CS5503.

V+

10 11 12

TP4

CLKIN (fig. 2)

BRCLK (fig. 2)

13 12 14 15 1

TP3

V+

INTCLK

EXTCLK

TP2

4.9152 MHz

CLKIN

TP1

74HC00

N= 0

910 11 12

Master Clock

Baud Clock

TP5

U1A

U1C

U1D

5.1 k

10 M

30 pF

200

0.1

µF

0.1

µF

74HC4040

U1B

Figure 1. Clock Generator

CDB5501/CDB5503

DS31DB3

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