LMS202ECMW datasheet(6/8 Pages) NSC

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Application Information (Continued)

MACHINE MODEL

The Machine Model is the standard ESD test method in

Japan and the automotive industry. It simulates a charge on

large object discharging through the IC device. This takes

place in automated test and handling systems. The equip-

ment can accumulate static charge due to improper ground-

ing, which is transmitted through the IC when it is picked and

placed.

The waveform is obtained by discharging 400V volts capaci-

tor to the device. Resistor, R2 = 0

Ω.

The parasitic inductance, L, from the PCB affects the peak

current and period of the waveform. For L = 0.5µF, the peak

current is approximately 7A with a period of 60 ns. For L =

2.5µH, the peak current is reduced to 4A with a period of 140

ns.

IEC 1000-4-2 (EN61000-4-2)

The European Union requires ESD immunity testing for all

electronic products as a condition for EMC Mark before

shipping to any member countries. This is not a IC require-

ment but an overall system requirement. IEC 1000-4-2

specifies ESD testing both by contact and air-gap discharge.

ESD testing by contact are generally more repeatable than

air-gap but is less realistic to actual ESD event. However,

air-gap discharge is more realistic but ESD results may vary

widely dependent on environmental conditions (temperature,

humidity,....) The waveform is obtained by discharging

150pF capacitor through a resistor, R2 = 330

Ω. A typical

peak current may be high as 37A with 10kV.

20048004

FIGURE 3. MM ESD Model

20048007

FIGURE 4. MM Waveform

20048004

FIGURE 5. IEC ESD Model

20048009

FIGURE 6. IEC Waveform

LMS202ECMW Arkusz danych(PDF) 6 Page - National Semiconductor (TI)