LPC804 datasheet(2/89 Pages) NXP

2 / 89 page

LPC804

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Product data sheet

Rev. 2.1 — 25 July 2023

2 of 87

NXP Semiconductors

LPC804

32-bit Arm Cortex-M0+ microcontroller



Supports Flash In-Application Programming (IAP).



Supports In-System Programming (ISP) through USART.



On-chip ROM APIs for integer divide.



Free Running Oscillator (FRO) API.



Digital peripherals:



High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 30

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, and input inverter. GPIO direction control

supports independent set/clear/toggle of individual bits.



High-current source output driver (20 mA) on five pins.



GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.



Switch matrix for flexible configuration of each I/O pin function.



CRC engine.



Capacitive Touch Interface.



Programmable Logic Unit (PLU) to create small combinatorial and/or sequential

logic networks including simple state machines.



Timers:



One 32-bit general purpose counter/timer, with four match outputs and three

capture inputs. Supports PWM mode, and external count



Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.



Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a

low-power, low-frequency internal oscillator, or an external clock input.



Windowed Watchdog timer (WWDT).



Analog peripherals:



One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports

two independent conversion sequences.



Comparator with five input pins and external or internal reference voltage.



One 10-bit DAC.



Serial peripherals:



Two USART interfaces with pin functions assigned through the switch matrix and

one fractional baud rate generators.



One SPI controllers with pin functions assigned through the switch matrix.



Two I2C-bus interface. It supports data rates up to 400 kbit/s on standard digital

pins.



Clock generation:



Free Running Oscillator (FRO). This oscillator provides a selectable

9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO

is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C

to 70 C.



1 MHz low power oscillator can be used as a clock source.



Clock output function with divider that can reflect all internal clock sources.



Power control:



Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and

deep power-down mode.

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