LTC2440IGN datasheet(17/28 Pages) LINER

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LTC2440

sn2440, 2440fas

APPLICATIO S I FOR ATIO

indicating the conversion result is ready. EOC = 1

(BUSY = 1) while the conversion is in progress and

EOC = 0 (BUSY = 0) once the conversion enters the low

power sleep state. On the falling edge of EOC/BUSY, the

conversion result is loaded into an internal static shift

first rising edge of SCK. Data is shifted out the SDO pin

on each falling edge of SCK enabling external circuitry to

latch data on the rising edge of SCK. EOC can be latched

on the first rising edge of SCK. On the 32nd falling edge

of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a

new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

EXT pin must be tied HIGH.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state. Alternatively,

BUSY (Pin 15) may be used to monitor the status of the

conversion in progress. BUSY is HIGH during the conver-

sion and goes LOW at the conclusion. It remains LOW until

the result is read from the device.

When testing EOC, if the conversion is complete (EOC = 0),

the device will exit the sleep state and enter the data output

state if CS remains LOW. In order to prevent the device

from exiting the low power sleep state, CS must be pulled

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time tEOCtest after the falling edge of CS

(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of tEOCtest is

500ns. If CS is pulled HIGH before time tEOCtest, the device

remains in the sleep state. The conversion result is held in

the internal static shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins on

Figure 8. Internal Serial Clock, Single Cycle Operation

SDO

BUSY

SCK

(INTERNAL)

MSB

SIG

BIT 0

LSB24

BIT 5

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2440 F08

<tEOCtest

Hi-Z

TEST EOC

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

VCC

REF+

REF–

SCK

BUSY

IN+

IN–

SDO

GND

EXT

1, 8, 9, 16

VCC

SDI

REFERENCE VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

µF

4.5V TO 5.5V

LTC2440

3-WIRE

SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION

10-SPEED/RESOLUTION PROGRAMMABLE

µV NOISE, 880Hz OUTPUT RATE

VCC

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