AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com)
Altima Communications Inc. reserves the right to make changes to this document without notice.
Document Revision 3.2
Page 7 of 37
RMII (Reduced Media Independent Interface) Pins
Pin Name
Pin #
Type
Description
TXD[1:0](0)
TXD[1:0](1)
TXD[1:0](2)
TXD[1:0](3)
84, 85
74, 75
60, 61
50, 51
I/O, D
I/O, D
I/O, D
I/O, D
RMII Transmit Data. The MAC will source TXD[1:0](n) synchronous with
REFCLK when TX_EN(n) is asserted.
TX_EN(0)
TX_EN(1)
TX_EN(2)
TX_EN(3)
86
76
63
53
I/O,D
I/O,D
I/O,D
I/O,D
RMII Transmit Enable. TX_EN(n) is asserted high by the MAC to indicate that
valid data for transmission is presented on the TXD[1:0](n).
RXD[1:0](0)
RXD[1:0](1)
RXD[1:0](2)
RXD[1:0](3)
78,79
68,69
55,56
45,46
I/O, D
I/O, D
I/O, D
I/O, D
RMII Receive Data. The Phy will source RXD[1:0](n) synchronous with
REFCLK when CRS_DV(n) is asserted.
CRS_DV(0)
CRS_DV(1)
CRS_DV(2)
CRS_DV(3)
82
71
58
48
I/O, D
I/O, D
I/O, D
I/O, D
CRS_DV(n) is asserted high when media is non-idle.
RX_ER(0)
RX_ER(1)
RX_ER(2)
RX_ER(3)
81
70
57
47
I/O, D
O
O
I/O, D
RMII Receive Error. When RX_ER is asserted high, it indicates an error has
been detected during frame reception.
REFCLK
66
I
Reference Clock Input – 50 MHz-100PPM TTL
SMI (Serial Management Inte rface) Pins
Pin Name
Pin #
Type
Description
MDIO
64
I/O, D
Management Data Input/Output. Bi-directional data interface. 1.5K pull up
resistor required (as specified in IEEE-802.3).
MDC
65
I, D
Management Data Clock. 0 to 25 MHz clock sourced by the MAC for transfer of
MDIO data.
INTR
94
Z
Interrupt. See Registers 16 and 17 for polarity and sources. The INTR pin has a
high impedance output, a 1K
Ω pull-up or pull-down resistor is needed.
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