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VV6410 Arkusz danych(PDF) 78 Page - STMicroelectronics |
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VV6410 Arkusz danych(HTML) 78 Page - STMicroelectronics |
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78 / 105 page ![]() VV5410 & VV6410 Serial Control Bus cd5410-6410f-3-0.fm Commercial in confidence 78/105 [112 - 113], [70-71] - Black Pixel Offset [114], [72] - Black Pixel Cancellation Setup Register [115], [73] - unused [116], [74] - reserved [117 - 118], [75-76] - Control Registers 0 and 1- CR0 and CR1 Although we give the user access to the following 5registers it is not anticipated that the contents of these registers will have to be altered. If the user does wish to alter any of the register bits then they are strongly advised to contact VIBU before doing so. Bit Function Default Comment 2:0 MS Black line pixel offset - 64 This register contains a fixed offset that can be applied to the digitised pixels in the digital output coding block.The offset is a 2’s complement number, giving an offset range -1024,+1023. If this external offset cancellation is to be applied then it register[114], bits[1:0] should be reprogrammed to 2’b1x. 7:0 LS Black line pixel offset Table 51 : [112 - 113], [70-71] - Black Pixel Offset Bit Function Default Comment 1:0 Black line offset cancellation 01 x0 - Accumulate black pixels, calculate black pixel average and report, but don’t apply anything to data stream 01 - Accumulate black pixels, calculate black pixel average and report and apply internally calculated offset to data stream 11 - Accumulate black pixels, calculate black pixel average and report, but apply an externally calculated offset 4:2 reserved 100 The time constant controls the rate at which a change in the black level is corrected for. 5 Use narrow black offset deadband Yes/No 1 The deadband describes a range of pixel averages that will cause the leaky integrator algorithm to hold it’s current value. 0 - Target +/- 4 codes 1 - Target +/- 2 codes 7:6 unused 00 Table 52 : [114], [72] - Black offset cancellation setup Bit Function Default Comment 0 Enable bit line clamp Off/On 0 1 Enable bit line test Off/On 0 Table 53 : [117], [75] - Control Register CR0 |
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