SL1461
5
FUNCTIONAL DESCRIPTION
The SL1461 is a wideband PLL FM demodulator, optimised
for application in satellite receiver systems and requiring a
minimum external component count. It contains all the
elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signal to correct for any frequency drift in the outdoor unit local
oscillator. A block diagram is contained in Fig. 2 and the typical
application in Fig. 3.
The internal pin connections are contained in Fig.6/6a.
In normal applications the second satellite IF frequency of
typically 402 or 479.5MHz is fed to the RF preamplifier, which
has a working sensitivity of typically –40 dBm, depending on
application and layout. The preamplifier contains an RF level
detect circuit, which generates an AGC signal that can be used
for controlling the gain of the IF amplifier stages, so
maintaining a fixed level to the RF input of the SL1461, for
optimum threshold performance. The bias point of the AGC
circuit can be adjusted to cater for variation in AGC line voltage
requirement and device input power. The typical AGC curves
are shown in Fig. 9.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which is
generated by an on–board oscillator. The oscillator block uses
an external varactor tuned sustaining network and is
optimised for high linearity over the normal deviation range. A
typical frequency versus voltage characteristic for the
oscillator is contained in Fig. 7. The loop output is designed to
compensate for first order temperature variation effects; the
typical stability is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic . Feedback can be applied either in differential
or single ended mode; if the appropriate phase detector gains
are assumed in calculating loop filters, both modes should
give the same loop response.
The loop amplifier drives a 75
W output impedance buffer
amplifier, which can either be connected to a 75
W load or used
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
DESIGN OF PLL LOOP PARAMETERS
Fig. 4
VCO
R2
C1
BASEBAND OUTPUT
R1
RF INPUT
GAIN = K0 RAD SEC/VOLT
GAIN = KD VOLT/RAD
The SL1461 is normally used as a type 1 second order loop
and can be represented by the above diagram. For such a
system the following parameters apply;
t
1 + C1.R1
t
2 + C1.R2
t
1 +
K
0KD
w2
n
t
2 +
2
z
wn
and
where:
K0 is the VCO gain in radian seconds per volt
KD is the phase detector gain in volts per radian
wn is the natural loop bandwidth
z is the loop damping factor
R1 is loop amplifier input impedance
Note:
KO is dependant on sensitivity of VCO used.
KD = 0.25V/rad single ended, 0.5V/rad differential
From these factors the loop 3dB bandwidth can be determined
from the following expression;
w23dB + w2n(2z2 ) 1) " w2n (2z2 ) 1)2 ) 1
w3dB + 2wn when z + 1
2
Which approximates to
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