M41ST84W datasheet(12/29 Pages) STMICROELECTRONICS

12 / 29 page

M41ST84W

12/29

WRITE Mode

In this mode the master transmitter transmits to

the M41ST84W slave receiver. Bus protocol is

shown in Figure 12., page 12. Following the

START condition and slave address, a logic '0' (R/

W=0) is placed on the bus and indicates to the ad-

dressed device that word address An will follow

and is to be written to the on-chip address pointer.

The data word to be written to the memory is

strobed in next and the internal address pointer is

incremented to the next memory location within

the RAM on the reception of an acknowledge

clock. The M41ST84W slave receiver will send an

acknowledge clock to the master transmitter after

it has received the slave address (see Figure

9., page 10) and again after it has received the

word address and each data byte.

Data Retention Mode

With valid VCC applied, the M41ST84W can be ac-

cessed as described above with READ or WRITE

cycles. Should the supply voltage decay, the

M41ST84W will automatically deselect, write pro-

tecting itself when VCC falls between VPFD(max)

and VPFD(min). This is accomplished by internally

inhibiting access to the clock registers. At this

time, the Reset pin (RST) is driven active and will

remain active until VCC returns to nominal levels.

When VCC falls below the Battery Back-up

Switchover Voltage (VSO), power input is switched

from the VCC pin to the external battery, and the

clock registers and SRAM are maintained from the

attached battery supply.

All outputs become high impedance. On power up,

when VCC returns to a nominal value, write protec-

tion continues for trec. The RST signal also re-

mains

active

during

this

time

(see

Figure

19., page 25).

For a further more detailed review of lifetime calcu-

lations, please see Application Note AN1012.

Figure 12. WRITE Mode Sequence

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

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